TOP: an algorithm for three-level combinational logic optimisation
2004 (English)In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 151, no 4, 307-314 p.Article in journal (Refereed) Published
Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type g(1degrees)g(2), where g(1) and g(2) are sum-of-products expressions and '(degrees)' is a binary operation. For the first time, to the authors' knowledge, this problem is addressed for an arbitrary operation '(degrees)', although several algorithms for specified cases of '(degrees)' have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser.
Place, publisher, year, edition, pages
2004. Vol. 151, no 4, 307-314 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-23789DOI: 10.1049/ip-cds:20040159ISI: 000224250100006ScopusID: 2-s2.0-5044249484OAI: oai:DiVA.org:kth-23789DiVA: diva2:342488
QC 201005252010-08-102010-08-102016-06-08Bibliographically approved