A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
2004 (English)In: Integration, ISSN 0167-9260, Vol. 38, no 1, 3-17 p.Article in journal (Refereed) Published
On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.
Place, publisher, year, edition, pages
2004. Vol. 38, no 1, 3-17 p.
IdentifiersURN: urn:nbn:se:kth:diva-23950DOI: 10.1016/j.vlsi.2004.03.005ISI: 000225668300002ScopusID: 2-s2.0-9544238123OAI: oai:DiVA.org:kth-23950DiVA: diva2:342649
QC 20100525 QC 201109222010-08-102010-08-102012-02-14Bibliographically approved