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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-8072-1742
KTH, Superseded Departments, Electronic Systems Design.
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
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2004 (English)In: Integration, ISSN 0167-9260, Vol. 38, no 1, 3-17 p.Article in journal (Refereed) Published
Abstract [en]

On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

Place, publisher, year, edition, pages
2004. Vol. 38, no 1, 3-17 p.
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-23950DOI: 10.1016/j.vlsi.2004.03.005ISI: 000225668300002Scopus ID: 2-s2.0-9544238123OAI: oai:DiVA.org:kth-23950DiVA: diva2:342649
Note
QC 20100525 QC 20110922Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2012-02-14Bibliographically approved

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Öberg, Johnny

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