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Notched-gate pMOSFET with ALD TiN/high-kappa gate stack formed by selective wet etching
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-6705-1660
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0002-5845-3032
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2004 (English)In: Electrochemical and solid-state letters, ISSN 1099-0062, E-ISSN 1944-8775, Vol. 7, no 10, G228-G230 p.Article in journal (Refereed) Published
Abstract [en]

Proof-of-concept notched-gate metal-oxide-semiconductor field-effect transistor (MOSFET) with the integration of atomic layer deposition (ALD) metal gate/high-kappa dielectric is demonstrated. The notched gate is formed by a combination of plasma dry etch and subsequent selective wet etch of a poly-Si0.7Ge0.3/TiN bilayer gate electrode stack. The height of the notch is determined mainly by the thickness of the TiN layer, and the width is controlled by the wet underetch of the TiN beneath the Si0.7Ge0.3 layer. Compared with reference MOS transistors with a similar gate stack, the notched gate pMOSFETs exhibited an expected reduction of the parasitic overlap capacitances.

Place, publisher, year, edition, pages
2004. Vol. 7, no 10, G228-G230 p.
Identifiers
URN: urn:nbn:se:kth:diva-24024DOI: 10.1149/1.1795612ISI: 000228539400043Scopus ID: 2-s2.0-8344243776OAI: oai:DiVA.org:kth-24024DiVA: diva2:342723
Note
QC 20100525Available from: 2010-08-10 Created: 2010-08-10 Last updated: 2017-12-12Bibliographically approved

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Hellström, Per-Erik

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