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Implementation and Verification of a CPU Subsystem for Multimode RF Transceivers
KTH, School of Information and Communication Technology (ICT).
2010 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Multimode transceivers are becoming a very popular implementation alternative because of their ability to support several standards on a single platform. For multimode transceivers, advanced control architectures are required to provide flexibility, reusability, and multi-standard support at low power consumption and small die area effort. In such an advance control architecture the CPU Subsystem functions as a central control unit which configures the transceiver and the interface for a particular communication standard.

Open source components are gaining popularity in the market because they not only reduce the design costs significantly but also provide power to the designer due to the availability of the full source code. However, open source architectures are usually available as poorly verified and untested intellectual properties (IPs). Before they can be commercially adapted, an extensive testing and verification strategy is required. In this thesis we have implemented a CPU Subsystem using open source components and performed the functional verification of this Subsystem. The main components of this CPU Subsystem are (i) an open source OpenRISC1200 core, (ii) a memory system, (iii) a triple-layer Sub-bus system and (iv) several Wishbone interfaces. The OpenRISC1200 core was used because it is a 32-bit core ideally suited for applications requiring high performance while having low-cost and low power consumption. The verification of a 5-stage pipeline processor is a challenging task and to the best of our knowledge this is the first attempt to verify the Open-RISC1200 core. The faults identified as a result of the functional verification will not only prove useful for the current project but will likelymake the OpenRISC1200 core a more reliable and commercially used processor.

Place, publisher, year, edition, pages
2010. , 179 p.
URN: urn:nbn:se:kth:diva-24270OAI: diva2:346202
Available from: 2010-08-31 Created: 2010-08-31 Last updated: 2010-08-31Bibliographically approved

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