Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE credits
In recent years, the research toward the development of high speed and high resolution analog-to-digital converters (ADCs) has been equally driven by the demand of high-speed wire line and wireless communication services. Delta-Sigma ADCs are widely used in wireless applications due to their oversampling and noise shaping characteristics.
This thesis aims to design a continuous-time sigma-delta modulator which can provide a dynamic range of 75 dB over a 25 MHz signal bandwidth. The proposed topology is a 4th order 3-bit low-pass sigma-delta modulator, which employs a combination of feedforward and feedback schemes. The design starts from system level using Matlab/Simulink. Then the behavioral level design is performed using Cadence VerilogA. Finally, the first integrator in the loop, which is the most critical block in the modulator, is implemented at transistor level using 90nm CMOS technology.
The most important non-idealities of the continuous time sigma-delta modulator, such as clock jitter, excess loop delay, DAC mismatch and time constant variance are considered. Their effects are analyzed and compensation techniques are proposed and introduced in the MATLAB models.
Combining all the issues, the modulator achieves the SNDR 75.02dB, dynamic range 77.58dB over signal bandwidth 25MHz at system level. The modulator with a SNDR 75.71 dB, dynamic range 76.14 dB over signal bandwidth 12.5MHz has been verified at system level together with the schematic design of the first integrator in 90nm CMOS technology.
2010. , 77 p.