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Bound set selection and circuit re-synthesis for area/delay driven decomposition
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.ORCID iD: 0000-0001-7382-9408
2005 (English)In: DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2005, 430-431 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses two problems related to disjoint-support decomposition of Boolean functions. First, we present a heuristic for finding a subset of variables, X, which results in the disjoint-support decomposition f(X, Y) = h(g(X), Y) with a good area/delay trade-off. Second, we present a technique for re-synthesis of the original circuit implementing f (X, Y) into a circuit implementing the decomposed representation h(g(x), Y)Preliminary experimental results indicate that the proposed approach has a significant potential.

Place, publisher, year, edition, pages
2005. 430-431 p.
Series
Design, Automation and Test in Europe Conference and Expo, ISSN 1530-1591
Keyword [en]
Boolean functions, Delay circuits, Electric network analysis, Electric variables control, Heuristic methods, Problem solving, Set theory
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-24442DOI: 10.1109/DATE.2005.83ISI: 000228086900079Scopus ID: 2-s2.0-33646918903ISBN: 0-7695-2288-2 (print)OAI: oai:DiVA.org:kth-24442DiVA: diva2:349904
Conference
Design, Automation and Test in Europe Conference and Exhibition (DATE 05) Munich, GERMANY, MAR 07-11, 2005
Note

QC 20100909

Available from: 2010-09-09 Created: 2010-09-09 Last updated: 2012-11-01Bibliographically approved
In thesis
1. Advances in Functional Decomposition: Theory and Applications
Open this publication in new window or tab >>Advances in Functional Decomposition: Theory and Applications
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

Functional decomposition aims at finding efficient representations for Boolean functions. It is used in many applications, including multi-level logic synthesis, formal verification, and testing.

This dissertation presents novel heuristic algorithms for functional decomposition. These algorithms take advantage of suitable representations of the Boolean functions in order to be efficient.

The first two algorithms compute simple-disjoint and disjoint-support decompositions. They are based on representing the target function by a Reduced Ordered Binary Decision Diagram (BDD). Unlike other BDD-based algorithms, the presented ones can deal with larger target functions and produce more decompositions without requiring expensive manipulations of the representation, particularly BDD reordering.

The third algorithm also finds disjoint-support decompositions, but it is based on a technique which integrates circuit graph analysis and BDD-based decomposition. The combination of the two approaches results in an algorithm which is more robust than a purely BDD-based one, and that improves both the quality of the results and the running time.

The fourth algorithm uses circuit graph analysis to obtain non-disjoint decompositions. We show that the problem of computing non-disjoint decompositions can be reduced to the problem of computing multiple-vertex dominators. We also prove that multiple-vertex dominators can be found in polynomial time. This result is important because there is no known polynomial time algorithm for computing all non-disjoint decompositions of a Boolean function.

The fifth algorithm provides an efficient means to decompose a function at the circuit graph level, by using information derived from a BDD representation. This is done without the expensive circuit re-synthesis normally associated with BDD-based decomposition approaches.

Finally we present two publications that resulted from the many detours we have taken along the winding path of our research.

Place, publisher, year, edition, pages
Stockholm: KTH, 2006. xi,176 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 06:06
Keyword
computer science, electronic system design, Boolean decomposition, binary decision diagram, logic synthesis, graph algorithm
National Category
Computer Science
Identifiers
urn:nbn:se:kth:diva-4135 (URN)
Public defence
2006-10-12, E, KTH Forum, Isafjordsgatan 39, Kista, 09:00
Opponent
Supervisors
Note
QC 20100909Available from: 2006-10-09 Created: 2006-10-09 Last updated: 2010-09-09Bibliographically approved

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Dubrova, Elena

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