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Size reduction of silicon nanopillars by photo-electrochemical etching
KTH, Superseded Departments, Electronics.
KTH, Superseded Departments, Electronics.ORCID iD: 0000-0002-5260-5322
2001 (English)In: Materials Research Society Symposium Proceedings, ISSN 0272-9172, Vol. 638, F851-F855 p.Article in journal (Refereed) Published
Abstract [en]

Silicon nanopillars, formed by electron beam lithography, were electrochemically etched to provide controlled size reduction. The smallest dimensions achieved were pillars of 15 nm in diameter, restricted mainly by the scanning electron microscope used for characterization. The etch rate was mainly determined by the photogeneration of carriers, by the HF concentration and by the applied voltage bias. The applied bias also controlled the resulting shape of the pillars such that a high bias resulted in etching of the pillar top whereas a negative bias caused etching only at the pillar base. For 0 V, a relatively conform etching of the pillar was observed. We discuss these phenomena in terms of electropolishing or pore formation effects on a local scale.

Place, publisher, year, edition, pages
2001. Vol. 638, F851-F855 p.
Keyword [en]
Characterization, Charge carriers, Electric potential, Electrochemistry, Electrolytic polishing, Electron beam lithography, Etching, Scanning electron microscopy, Silicon, Photo-electrochemical etching, Nanostructured materials
National Category
Condensed Matter Physics
URN: urn:nbn:se:kth:diva-25817OAI: diva2:359948
QC 20101101Available from: 2010-11-01 Created: 2010-11-01 Last updated: 2010-11-01Bibliographically approved
In thesis
1. Silicon nanowires, nanopillars and quantum dots: Fabrication and characterization
Open this publication in new window or tab >>Silicon nanowires, nanopillars and quantum dots: Fabrication and characterization
2005 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

Semiconductor nanotechnology is today a very well studied subject, and demonstrations of possible applications and concepts are abundant. However, well-controlled mass-fabrication on the nanoscale is still a great challenge, and the lack of nanofabrication methods that provide the combination of required fabrication precision and high throughput, limits the large-scale use of nanodevices. This work aims in resolving some of the issues related to nanostructure fabrication, and deals with development of nanofabrication processes, the use of size-reduction for reaching true nanoscale dimensions (20 nm or below), and finally the optical and electrical characterization to understand the physics of the more successful structures and devices in this work. Due to its widespread use in microelectronics, silicon was the material of choice throughout this work.

Initially, a fabrication process based on electron beam lithography (EBL) was designed, allowing controlled fabrication of devices of dimensions down to 30 nm, although, generally, initial device dimensions were above 70 nm, allowing the flexible but low-throughput EBL, to be replaced by state-of-the-art optical lithography in the case of industrialization of the process. A few main processes were developed throughout the course of this work, which were capable of defining silicon nanopillar and nano-wall arrays from bulk silicon, and silicon nanowire devices from silicon-on-insulator (SOI) material.

Secondly, size-reduction, as a means of providing access to few-nanometer dimensions not available by current lithography techniques was investigated. An additional goal of the size-reduction studies was to find self-limiting mechanisms in the process, that would limit the impact of variations in the size and other imperfections of the initial structures. Thermal oxidation was investigated mainly for self-limited size-reduction of silicon nanopillars, resulting in well-defined quantum dot arrays of few-nm dimensions. Electrochemical etching was employed to size-reduce both silicon nanopillars and silicon nanowires down into the 10-nm regime. This being a novel application, a more thorough study of electrochemical etching of low-dimensional and thin-layer structures was performed as well as development of a micro-electrochemical cell, enabling electrochemical etching of fabricated nanowire devices with improved control.

Finally, the combination of nanofabrication and size-reduction resulted in two successful device structures: Sparse and spatially well-controlled single silicon quantum dot arrays, and electrically connected size-reduced silicon nanowires. The quantum dot arrays were investigated through photoluminescence spectroscopy demonstrating for the first time atomic-like photoemission from single silicon quantum dots. The silicon nanowire devices were electrically characterized. The current transport through the device was determined to be through inversion layer electrons with surface states of the nanowire surfaces greatly affecting the conductance of the nanowire. A model was also proposed, capable of relating physical and electrical properties of the nanowires, as well as demonstrating the considerable influence of charged surface states on the nanowire conductance.

Place, publisher, year, edition, pages
Stockholm: KTH, 2005. ix, 98 p.
Trita-FTE, ISSN 0284-0545 ; 2005:4
Silicon nanowires, silicon nanopillars, silicon quantum dots, size-reduction, thermal oxidation, electrochemical etching of silicon, photoluminescence
National Category
Condensed Matter Physics
urn:nbn:se:kth:diva-420 (URN)
Public defence
2005-09-27, C1, KTH-Electrum, Isafjordsgatan 26, Kista, 10:15
QC 20101101Available from: 2005-09-15 Created: 2005-09-15 Last updated: 2010-11-01Bibliographically approved

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