Analysis of Worst-Case Delay Bounds for On-Chip Packet-Switching Networks
2010 (English)In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, Vol. 29, no 5, 802-815 p.Article in journal (Refereed) Published
In network-on-chip (NoC), computing worst-case delay bounds for packet delivery is crucial for designing predictable systems but yet an intractable problem. This paper presents an analysis technique to derive per-flow communication delay bound. Based on a network contention model, this technique, which is topology independent, employs network calculus to first compute the equivalent service curve for an individual flow and then calculate its packet delay bound. To exemplify this method, this paper also presents the derivation of a closed-form formula to compute a flow's delay bound under all-to-one gather communication. Experimental results demonstrate that the theoretical bounds are correct and tight.
Place, publisher, year, edition, pages
2010. Vol. 29, no 5, 802-815 p.
Delay bound, network calculus, network-on-chip, performance analysis, quality-of-service
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-27508DOI: 10.1109/TCAD.2010.2043572ISI: 000278502500012ScopusID: 2-s2.0-77951675199OAI: oai:DiVA.org:kth-27508DiVA: diva2:386079
QC 201101122011-01-122010-12-132011-01-12Bibliographically approved