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 Leon3 NoC System Generator
KTH, School of Information and Communication Technology (ICT).
2010 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

In order to meet challenges of today’s computation extensive SoC applications, there is a need to have more processors on a chip than ever before. Network on Chip (NoC) is a new paradigm to meet these challenges. It provides high computation power by incorporating multiple processors on a single integrated circuit (IC) in the form of a network. The NoC provides high bandwidth and high computation power and avoids the problems faced by using conventional bus systems. The NoC designs are developed so far by using design tools and platform of different venders. Each has their strict license policies and development limitations. With the advent of the NoC, there arises a need to make NoC based systems more efficient as well as low cost. To achieve this goal, the NoC systems must be made technology independent, by using the freely available opencores and opensource processors and IP cores. The Leon3 processor developed by AeroFlex Gaisler is a good choice for this purpose. The Leon3 uses the AMBA bus to connect to different peripherals and IP cores that are also provided by AeroFlex Gaisler in the form of a library. The thesis is targeted to migrate from the existing multi-core 4x4 NoC system that is based on Nios II processor and developed by KTH to the 2D Mesh 2x2 NoC system that is based on Leon3 processor. There is also provided a Graphical User Interface (GUI) to generate the Leon3 NoC system.

Place, publisher, year, edition, pages
2010. , 80 p.
URN: urn:nbn:se:kth:diva-28757OAI: diva2:389745
Available from: 2011-01-20 Created: 2011-01-20 Last updated: 2011-01-20Bibliographically approved

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