Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Surface-passivation effects on the performance of 4H-SiC BJTs
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
Show others and affiliations
2011 (English)In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, 259-265 p.Article in journal (Refereed) Published
Abstract [en]

In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

Place, publisher, year, edition, pages
2011. Vol. 58, 259-265 p.
Keyword [en]
Bipolar junction transistor; Breakdown voltage; Current gains; Device simulations; Electrical performance; High-voltages; Interface traps; Oxide charge; Passivation effect; Passivation layer; power transistor; Surface passivation, Electric breakdown; MOS capacitors; Passivation; Power electronics; Silicon carbide; Silicon oxides; Silicon wafers; Tunnel diodes, Bipolar transistors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-29778DOI: 10.1109/TED.2010.2082712ISI: 000285840100034Scopus ID: 2-s2.0-78650871047OAI: oai:DiVA.org:kth-29778DiVA: diva2:397724
Note
QC 20110215Available from: 2011-02-15 Created: 2011-02-15 Last updated: 2017-12-11Bibliographically approved
In thesis
1. Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
Open this publication in new window or tab >>Fabrication Technology for Efficient High Power Silicon Carbide Bipolar Junction Transistors
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The superior characteristics of Silicon Carbide as a wide band gap semiconductor have motivated many industrial and non-industrial research groups to consider SiC for the next generations of high power semiconductor devices. The SiC Bipolar Junction Transistor (BJT) is one candidate for high power applications due to its low on-state power loss and fast switching capability. However, to compete with other switching devices such as Field Effect Transistors (FETs) or IGBTs, it is necessary for a power SiC BJT to provide a high current gain to reduce the power required from the drive circuit. In this thesis implantation free 4H-SiC BJTs with linearly graded base layer have been demonstrated with common-emitter current gain of 50 and open-base breakdown voltage of 2700 V. Also an efficient junction termination extension (JTE) with 80% of theoretical parallel-plane breakdown voltage was analyzed by fabrication of high voltage PiN diodes to achieve an optimum dose of remaining JTE charge. Surface passivation of 4H-SiC BJT is an essential factor for efficient power BJTs. Therefore different passivation techniques were compared and showed that around 60% higher maximum current gain can be achieved by a newsurface passivation layer with low interface trap density that consists of PECVD oxide followed by post-deposition oxide anneal in N2O ambient. This surface passivation along with doublezone JTE were used for fabrication of high power BJTs that result in successful demonstration of 2800 V breakdown voltage for small area (0.3 × 0.3 mm) and large area (1.8 × 1.8 mm) BJTs with a maximum dc current gain of 55 and 52, respectively. The small area BJT showed RON = 4mΩcm2, while for the large are BJT RON = 6.8 mΩcm2. Finally, a Darlington transistor with a maximum current gain of 2900 at room temperature and 640 at 200 °C is reported. The high current gain of the Darlington transistor is achieved by optimum design for the ratio of the active area of the driver BJT to the output BJT.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xv, 79 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:01
National Category
Electrical Engineering, Electronic Engineering, Information Engineering Other Engineering and Technologies not elsewhere specified
Identifiers
urn:nbn:se:kth:diva-29726 (URN)978-91-7415-861-8 (ISBN)
Public defence
2011-03-04, Sal C1, KTH-Electrum, Isafjordsgatan 22, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20110216Available from: 2011-02-16 Created: 2011-02-14 Last updated: 2011-02-16Bibliographically approved
2. Fabrication and Characterization of 3C- and4H-SiC MOSFETs
Open this publication in new window or tab >>Fabrication and Characterization of 3C- and4H-SiC MOSFETs
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

During the last decades, a global effort has been started towards the implementation of energy efficient electronics. Silicon carbide (SiC), a wide band-gap semiconductor is one of the potential candidates to replace the widespread silicon (Si) which enabled and dominates today’s world of electronics. It has been demonstrated that devices based on SiC lead to a drastic reduction of energy losses in electronic systems. This will help to limit the global energy consumption and the introduction of renewable energy generation systems to a competitive price.

Active research has been dedicated to SiC since the 1980’s. As a result, a mature SiC growth technology has been developed and 4 inch SiC wafers are today commercially available. Research and development activities on the fabrication of SiC devices have also been carried out and resulted in the commercialization of SiC devices. In 2011, Schottky barrier diodes, bipolar junction transistors, and junction field effect transistors can be purchased from several electronic component manufacturers.

However, the device mostly used in electronics, the metal-oxide-semiconductor field effect transistor (MOSFET) is only recently commercially available in SiC. This delay is due to critical technology issues related to reliability and stability of the device, which still challenge many researchers all over the world.

This thesis summarizes the main challenges of the SiC MOSFET fabrication process. State of the art technology modules like the gate stack formation, the drain/source ohmic contact formation, and the passivation layer deposition are considered and contributions of this work to the development of these technology modules is reported.

The investigated technology modules are integrated into the complete fabrication process of vertical MOSFET devices. This MOSFET process was tested using cubic SiC (3C-SiC) and hexagonal SiC (4H-SiC) wafers and achieved results will be discussed.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xviii, 97 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:05
Keyword
SiC, MOSFETs, Fabrication, Characterization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
SRA - ICT
Identifiers
urn:nbn:se:kth:diva-32367 (URN)978-91-7415-913-4 (ISBN)
Public defence
2011-05-06, Sal C1, KTH-Electrum, Isafjordsgatan 22, Kista, 11:38 (English)
Opponent
Supervisors
Funder
EU, FP7, Seventh Framework Programme, MRTN-CT-2006-035735
Note
QC 20110415Available from: 2011-04-15 Created: 2011-04-13 Last updated: 2011-04-29Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopus

Authority records BETA

Zetterling, Carl-Mikael

Search in DiVA

By author/editor
Ghandi, RezaBuono, BenedettoDomeij, MartinEsteve, RomainSchöner, AdolfReshanov, Sergey A.Zetterling, Carl-MikaelÖstling, Mikael
By organisation
Integrated Devices and Circuits
In the same journal
IEEE Transactions on Electron Devices
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 444 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf