Trends of Terascale Computing Chips in the Next Ten Years
2009 (English)In: 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS / [ed] Tang TA; Zeng XY; Chen Y; Yu HH, NEW YORK: IEEE , 2009, 62-66 p.Conference paper (Refereed)
Moore's law steadily continues though facing a number of challenges. This paper identifies ongoing and desirable trends to exploit the technology capacity and flirt her Moore 's law for terascale on-chip computing architectures in the next ten years. Four foreseeable trends are: from single core to many cores, from bus-based to network-based interconnect, from centralized memory to distributed memory, and from 2D integration to 3D integration. We motivate these trends and show that the number of design choices for computing chips is increasing rapidly, leading to an exploding design space with uncountable opportunities for the innovative architect. Moreover, we envision that the multicore Network-on-Chip will become an infrastructure backbone and accumulate many other infrastructural functions such as memory, power and resource management, testing and diagnostic services.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2009. 62-66 p.
Computer Architecture, Network-on-Chip, Multi-core System, Distributed Memory, 3D Integration
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-29927DOI: 10.1109/ASICON.2009.5351607ISI: 000275924100012ScopusID: 2-s2.0-77949365761OAI: oai:DiVA.org:kth-29927DiVA: diva2:398417
IEEE 8th International Conference on ASIC, Changsha, PEOPLES R CHINA, OCT 20-23, 2009
QC 201102172011-02-172011-02-172011-02-17Bibliographically approved