Partially Reconfigurable Interconnection Network for Dynamically Reprogrammable Resource Array
2009 (English)In: 2009 IEEE 8TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS / [ed] Tang TA; Zeng XY; Chen Y; Yu HH, NEW YORK: IEEE , 2009, 122-125 p.Conference paper (Refereed)
This paper describes an innovative regular non-blocking, point-to-point, point-to-multipoint, low latency interconnection network scheme with sliding window connectivity, which allows arbitrary parallelism among large sub-systems. The area overhead of interconnect is only 30% of the chip area which is much smaller as compared to 80% in case of FPGA. The interconnection scheme is partially and dynamically reconfigurable. The configware is reduced 5.6 times by using binary encoding which allows energy efficient dynamic reconfiguration(1).
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2009. 122-125 p.
Interconnects, CGRA, Partially Reconfigurable, Dynamically Reconfigurable
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-29928DOI: 10.1109/ASICON.2009.5351593ISI: 000275924100026ScopusID: 2-s2.0-77949370051OAI: oai:DiVA.org:kth-29928DiVA: diva2:398422
IEEE 8th International Conference on ASIC, Changsha, PEOPLES R CHINA, OCT 20-23, 2009
QC 201102172011-02-172011-02-172012-01-12Bibliographically approved