Circuit Modeling of Vertical Buried-Grid SiC JFETs
2010 (English)In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2 / [ed] Bauer AJ; Friedrichs P; Krieger M; Pensl G; Rupp R; Seyller T, 2010, Vol. 645-648, 965-968 p.Conference paper (Refereed)
The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JEET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.
Place, publisher, year, edition, pages
2010. Vol. 645-648, 965-968 p.
, Materials Science Forum, ISSN 0255-5476 ; 645-648
JFET modeling, Vertical Buried-Grid SIC JFET, SiC JFET, PSpice, Medici
IdentifiersURN: urn:nbn:se:kth:diva-29665DOI: 10.4028/www.scientific.net/MSF.645-648.965ISI: 000279657600230ScopusID: 2-s2.0-77955442320OAI: oai:DiVA.org:kth-29665DiVA: diva2:398956
13th International Conference on Silicon Carbide and Related Materials
QC 201102212011-02-212011-02-112011-02-21Bibliographically approved