A Flow Regulator for On-Chip Communication
2009 (English)In: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS / [ed] Sezer S; Marshall A; Buechner T, 2009, 151-154 p.Conference paper (Refereed)
We have proposed (sigma, rho)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where sigma bounds the traffic burstiness and rho the traffic rate. In this paper, we present a hardware implementation of the regulator. We discuss its microarchitecture. Based on this microarchitecture, we design, implement and synthesize a multi-flow regulator for AXI. Our experiments show the effectiveness of such a regulation device on the control of delay, jitter and buffer requirements.
Place, publisher, year, edition, pages
2009. 151-154 p.
, IEEE International SOC Conference
Buffer requirements, Control quality, Effective communication, Flow regulation, Hardware implementations, Micro architectures, On chip communication, System-On-Chip, Traffic burstiness, Traffic rate, Application specific integrated circuits, Hardware, Jitter, Microprocessor chips, Programmable logic controllers
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-29859DOI: 10.1109/SOCCON.2009.5398072ISI: 000277503200031ScopusID: 2-s2.0-77949645911ISBN: 978-1-4244-5220-0OAI: oai:DiVA.org:kth-29859DiVA: diva2:399550
IEEE International SOC Conference, Belfast, NORTH IRELAND, SEP 09-11, 2009
QC 201102222011-02-222011-02-172012-03-20Bibliographically approved