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High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-4859-3100
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2009 (English)In: 2009 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, 2009, 2985-2988 p.Conference paper, Published paper (Refereed)
Abstract [en]

We propose a novel design estimation method for adaptive streaming applications to be implemented on a partially reconfigurable FPGA. Based on experimental results we enable accurate design cost estimates at an early design stage. Given the size and computation time of a set of configurations, which can be derived through logic synthesis, our method gives estimates for configuration parameters, such as bitstream sizes, computation mid reconfiguration times. To fulfil the system's throughput requirements, the required FIFO buffer sizes are then calculated using a hybrid analysis approach based on integer linear programming and simulation. Finally, we are able to calculate the total design cost as the sum of the costs for the FPGA area, the required configuration memory and the FIFO buffers. We demonstrate our method by analysing non-obvious trade-offs for a static and dynamic implementation of adaptivity.

Place, publisher, year, edition, pages
2009. 2985-2988 p.
Series
International Parallel and Distributed Processing Symposium (IPDPS), ISSN 1530-2075
Keyword [en]
Accurate design, Adaptivity, Bit stream, Computation time, Configuration memory, Configuration parameters, Design costs, Early design stages, Estimation methods, FIFO buffer, High-level estimation, Hybrid analysis, Integer Linear Programming, Logic synthesis, Novel design, Reconfigurable FPGA, Static and dynamic, Streaming applications, Trade-off analysis, Cost accounting, Design, Distributed parameter networks, Field programmable gate arrays (FPGA), Integer programming, Linearization, Real time systems
National Category
Computer Science
Identifiers
URN: urn:nbn:se:kth:diva-30379DOI: 10.1109/IPDPS.2009.5161208ISI: 000272993601140Scopus ID: 2-s2.0-70449868810ISBN: 978-1-4244-3751-1 (print)OAI: oai:DiVA.org:kth-30379DiVA: diva2:401300
Conference
23rd IEEE International Parallel and Distributed Processing Symposium, Rome, ITALY, MAY 23-29, 2009
Note

QC 20110302

Available from: 2011-03-02 Created: 2011-02-24 Last updated: 2016-05-18Bibliographically approved

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Sander, Ingo

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