Flow Regulation for On-Chip Communication
2009 (English)In: DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, 2009, 578-581 p.Conference paper (Refereed)
We propose (sigma, rho)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where sigma bounds the traffic burstiness and rho the traffic rate. This regulation changes the burstiness and timing of traffic flows, and can be used to decrease delay and reduce buffer requirements in the SoC infrastructure. In this paper, we define and analyze the regulation spectrum, which bounds the upper and lower limits of regulation. Experiments on a Network-on-Chip (NoC) with guaranteed service demonstrate the benefits of regulation We conclude that flow regulation may exert significant positive impact on communication performance and buffer requirements.
Place, publisher, year, edition, pages
2009. 578-581 p.
, Design, Automation and Test in Europe Conference and Expo, ISSN 1530-1591
Buffer requirements, Burstiness, Communication performance, Control quality, Effective communication, Flow regulation, Guaranteed service, Lower limits, Network on chip, On chip communication, System-On-Chip, Traffic burstiness, Traffic flow, Traffic rate, Application specific integrated circuits, Electric network topology, Microprocessor chips, Traffic surveys
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-30351ISI: 000273246700104ScopusID: 2-s2.0-70350053135ISBN: 978-1-4244-3781-8OAI: oai:DiVA.org:kth-30351DiVA: diva2:401569
Design, Automation and Test in Europe Conference and Exhibition, Nice, FRANCE, APR 20-24, 2009
QC 201103032011-03-032011-02-242011-03-03Bibliographically approved