Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits
2009 (English)In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, NEW YORK: IEEE , 2009, 322-329 p.Conference paper (Refereed)
Modeling parasitic parameters of Through-Silicon-Via (TSV) structures is essential in exploring electrical characteristics such as delay and signal integrity (SI) of circuits and interconnections in three-dimensional (3-D) Integrated Circuits (ICs). This paper presents a complete set of self-consistent equations including self and coupling terms for resistance, capacitance and inductance of various TSV structures. Further, a reduced-order electrical circuit model is proposed for isolated TSVs as well as bundled structures for delay and SI analysis, and extracted TSV parasitics are employed in Spectre simulations for performance evaluations. Critical issues in the performance modeling for design space exploration of 3-D ICs such as crosstalk induced switching pattern dependent delay variation and cross-talk on noise are discussed. The error in these metrics when using the proposed models as compared to a field solver is contained to a few percentage points.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2009. 322-329 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-30157DOI: 10.1109/3DIC.2009.5306541ISI: 000275055600060ScopusID: 2-s2.0-70549084864ISBN: 978-1-4244-4511-0OAI: oai:DiVA.org:kth-30157DiVA: diva2:401800
IEEE International Conference on 3D Systems Integration San Francisco, CA, SEP 28-30, 2009
QC 201103032011-03-042011-02-212012-02-12Bibliographically approved