3-D Memory Organization and Performance Analysis for Multi-processor Network-On-Chip Architecture
2009 (English)In: 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, NEW YORK: IEEE , 2009, 42-48 p.Conference paper (Refereed)
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid state drives - (SSD) such as flash memories replacing HDDs and multi-processor memory system realized in a single 3-D structure with network-on-chip (NOC) architecture as a communication medium. This paper discusses high level memory organization and architectural modeling and simulation based on 3-D NOC. A comparative analysis among several models including Dance-hall, Sandwich, Terminal, Per-layer and mixed architectures is done. Simulations in cycle accurate 3-D NOC VHDL model are done to evaluate the performance each architecture in uniform and local traffic patterns.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2009. 42-48 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-30156DOI: 10.1109/3DIC.2009.5306593ISI: 000275055600008ScopusID: 2-s2.0-70549091100ISBN: 978-1-4244-4511-0OAI: oai:DiVA.org:kth-30156DiVA: diva2:401802
IEEE International Conference on 3D Systems Integration San Francisco, CA, SEP 28-30, 2009
QC 201103032011-03-042011-02-212015-12-21Bibliographically approved