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Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2008 (English)In: PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY / [ed] Johansson LSO, Andersen JN, Gothelid M, Helmersson U, Montelius L, Rubel M, Setina J, Wernersson LE, Bristol: IOP PUBLISHING LTD , 2008, Vol. 100Conference paper, Published paper (Refereed)
Abstract [en]

In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si) and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by means of atomic force microscopy in combination with an elaborated sample preparation technique that allowed the LER at different depths of the sidewall to be measured. Samples were patterned by I-line lithography and etching was performed at an RF power of 200 W using HBr/Cl-2 (30/10 sccm) plasma. For sc-Si the photoresist and Si sidewalls had an LER of 0.8-1.4 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the photoresist sidewall roughness was, respectively, increased to 1.5-3 nm and 2-3.5 nm due to light scattering from the rough surface of the polycrystalline materials. The poly-Si film had a sidewall roughness of 3-4 nm. Poly-SiGe sidewall exhibited larger roughness with an LER of 5-12 nm which was not transferred from the photoresist. The results show that for sc-Si and poly-Si the sidewall roughness mainly originates from the photoresist process and little additional roughening is caused by the HBr/Cl-2 etching. However, for poly-Si0.2Ge0.8 the LER is considerably increased from that of the photoresist indicating that the HBr/Cl-2 etching is the main contributor to the LER.

Place, publisher, year, edition, pages
Bristol: IOP PUBLISHING LTD , 2008. Vol. 100
Series
Journal of Physics Conference Series, ISSN 1742-6588 ; 100
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-30139DOI: 10.1088/1742-6596/100/6/062021ISI: 000275655200217Scopus ID: 2-s2.0-77954331895OAI: oai:DiVA.org:kth-30139DiVA: diva2:401903
Conference
17th International Vacuum Congress/13th International Conference on Surface Science/Internatinal Conference on Nanoscience and Technology Stockholm, SWEDEN, JUL 02-06, 2007
Note
QC 20110909Available from: 2011-03-04 Created: 2011-02-21 Last updated: 2011-12-06Bibliographically approved
In thesis
1. Fabrication, characterization, and modeling of metallic source/drain MOSFETs
Open this publication in new window or tab >>Fabrication, characterization, and modeling of metallic source/drain MOSFETs
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS).

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:15
Keyword
Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate, FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-49184 (URN)978-91-7501-161-5 (ISBN)
Public defence
2011-12-16, Sal / Hall C2, KTH-Electrum, Isafjordsgatan 26, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20111206Available from: 2011-12-06 Created: 2011-11-25 Last updated: 2011-12-06Bibliographically approved

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Hellström, Per-Erik

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