Towards Schottky-Barrier Source/Drain MOSFETs
2008 (English)In: 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4 / [ed] Yu M, An X, NEW YORK: IEEE , 2008, 146-149 p.Conference paper (Refereed)
This paper provides an overview of metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology. The technology offers several benefits for scaling CMOS, i.e., extremely low source/drain resistance, sharp junctions from S/D to channel and low temperature processing. A successful implementation of the technology needs to overcome new obstacles such as SB height engineering and precise control of silicide growth. Device design factors such as S/D to gate underlap, Si film thickness and oxide thickness affect device performance owing to their effects on the SB width. In the past two years several groups have demonstrated high-performance SB MOSFETs, which places the technology as a promising candidate for future generations of CMOS technology.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2008. 146-149 p.
thin-body soi, dopant segregation, performance, devices, transistors, technology, finfets
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-30859DOI: 10.1109/ICSICT.2008.4734492ISI: 000265971000038ScopusID: 2-s2.0-60649112513ISBN: 978-1-4244-2185-5OAI: oai:DiVA.org:kth-30859DiVA: diva2:402157
9th International Conference on Solid-State and Integrated-Circuit Technology Beijing, PEOPLES R CHINA, OCT 20-23, 2008
QC 201103072011-03-072011-03-042011-03-07Bibliographically approved