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Characterization of dopant segregated Schottky barrier source/drain contacts
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0001-6705-1660
KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0002-5845-3032
2009 (English)In: ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON / [ed] Mantl S, Lemme M, Schubert J, Albrecht W, NEW YORK: IEEE , 2009, 73-76 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, the gate-voltage dependent source/drain (S/D) resistance (R-SD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of R-SD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.

Place, publisher, year, edition, pages
NEW YORK: IEEE , 2009. 73-76 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-30831DOI: 10.1109/ULIS.2009.4897542ISI: 000266761300018Scopus ID: 2-s2.0-67650655703ISBN: 978-1-4244-3705-4 (print)OAI: oai:DiVA.org:kth-30831DiVA: diva2:403020
Conference
10th International Conference on Ultimate Integration on Silicon Aachen, GERMANY, MAR 18-20, 2009
Note
QC 20110310Available from: 2011-03-10 Created: 2011-03-04 Last updated: 2011-12-06Bibliographically approved
In thesis
1. Fabrication, characterization, and modeling of metallic source/drain MOSFETs
Open this publication in new window or tab >>Fabrication, characterization, and modeling of metallic source/drain MOSFETs
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS).

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xii, 78 p.
Series
Trita-ICT/MAP AVH, ISSN 1653-7610 ; 2011:15
Keyword
Metallic source/drain, contact resistivity, Monte Carlo, NiSi, PtSi, SOI, UTB, tri-gate, FinFET, multiple-gate, nanowire, MOSFET, CMOS, Schottky barrier, silicide, SALICIDE
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-49184 (URN)978-91-7501-161-5 (ISBN)
Public defence
2011-12-16, Sal / Hall C2, KTH-Electrum, Isafjordsgatan 26, Kista, 10:00 (English)
Opponent
Supervisors
Note
QC 20111206Available from: 2011-12-06 Created: 2011-11-25 Last updated: 2011-12-06Bibliographically approved

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Hellström, Per-Erik

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