Pulse Latch Based FSRs for Low-Overhead Hardware Implementation of Cryptographic Algorithms
2010 (English)In: 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, 253-259 p.Conference paper (Refereed)
In this paper, we address the problem of low-overhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flip-flop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power.
Place, publisher, year, edition, pages
2010. 253-259 p.
, Proceedings IEEE International Conference on Computer Design, ISSN 1063-6404
Channel length, Clock frequency, Cryptographic algorithms, Feedback shift register, Hardware implementations, Power consuming, Reduction in area, Static time, Stream Ciphers, Total power, Flip flop circuits, Hardware, Shift registers
Computer Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-31395DOI: 10.1109/ICCD.2010.5647756ISI: 000286933700036ScopusID: 2-s2.0-78650750742ISBN: 978-1-4244-8935-0OAI: oai:DiVA.org:kth-31395DiVA: diva2:403470
IEEE International Conference on Computer Design, Amsterdam, NETHERLANDS, OCT 03-06, 2010
QC 201103142011-03-142011-03-142011-03-14Bibliographically approved