Lowering the Latency of Interfaces for Rationally-Related Frequencies
2010 (English)In: 2010 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, 2010, 23-30 p.Conference paper (Refereed)
We have introduced the Globally-Ratiochronous, Locally-Synchronous (GRLS) design paradigm, a design style based on rationally-related frequencies, with the objective to overcome the limitations of traditional multi-frequency systems by providing a flexibility close that of Globally-Asynchronous, Locally-Synchronous (GALS) systems but introducing performance penalties and overheads close to those of mesochronous systems. In this paper we focus on performances and improve the latency figures of our original GRLS interfaces by introducing two new interfaces, called GRLS-F and GRLS-noF, the first suitable for blocks with long computation time and the second for blocks with short computation time. The latency figures of the original GRLS interfaces are improved up to 50% without increasing complexity. The average latency figures of the resulting interfaces are lower than 1 Receiver clock cycle, the latency of a synchronous interface.
Place, publisher, year, edition, pages
2010. 23-30 p.
, Proceedings IEEE International Conference on Computer Design, ISSN 1063-6404
Clock cycles, Computation time, Design paradigm, Design styles, Mesochronous, Multi frequency, Performance penalties, Synchronous interface
Computer Engineering Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-31394DOI: 10.1109/ICCD.2010.5647563ISI: 000286933700004ScopusID: 2-s2.0-78650752605ISBN: 978-1-4244-8935-0OAI: oai:DiVA.org:kth-31394DiVA: diva2:403473
IEEE International Conference on Computer Design, Amsterdam, NETHERLANDS, OCT 03-06, 2010
QC 201103142011-03-142011-03-142011-03-14Bibliographically approved