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A General Approach to High-Level Energy and Performance Estimation in SoCs
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0565-9376
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2009 (English)In: 22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS   , 2009, 200-205 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present a high-level methodology for efficient and accurate estimation of energy and performance in SoCs at Functional Untimed Level. We then validate the proposed method against gate level for accuracy and against TLM-PV for speed. We show that the method is within 15% of gate-level accuracy and in aver-age 28x faster than TLM-PV, for the benchmark applications selected.

Place, publisher, year, edition, pages
2009. 200-205 p.
Series
International Conference on VLSI Design, Proceedings, ISSN 1063-9667
Keyword [en]
Benchmarking, Integrated circuits, Accurate estimations, Benchmark applications, Gate levels, General approaches, Performance estimations
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-31219DOI: 10.1109/VLSI.Design.2009.25ISI: 000264822300034ISBN: 978-0-7695-3506-7 (print)OAI: oai:DiVA.org:kth-31219DiVA: diva2:405990
Conference
22nd International Conference on VLSI Design held with 8th International Conference on Embedded Systems, New Delhi, INDIA, JAN 05-09, 2009
Note
QC 20110324Available from: 2011-03-24 Created: 2011-03-11 Last updated: 2011-03-24Bibliographically approved

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Hemani, Ahmed

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CiteExportLink to record
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Citation style
  • apa
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  • Other locale
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