A 60 GHz receiver front-end in 65 nm CMOS
2011 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, no 1, 61-71 p.Article in journal (Refereed) Published
In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.
Place, publisher, year, edition, pages
2011. Vol. 67, no 1, 61-71 p.
Receiver front-end, EM simulation, mm-wave transistor model, mm-wave inductor model, 60 GHz CMOS circuit design
IdentifiersURN: urn:nbn:se:kth:diva-31902DOI: 10.1007/s10470-010-9510-8ISI: 000288165500008ScopusID: 2-s2.0-79953178932OAI: oai:DiVA.org:kth-31902DiVA: diva2:406917
QC 201102292011-03-292011-03-282011-03-29Bibliographically approved