An ASIC-Design-Based Configurable SOC Architecture for Networked Media
2008 (English)In: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi J, Takala J, Vainio O, NEW YORK: IEEE , 2008, 41-44 p.Conference paper (Refereed)
An ASIC-design-based configurable SOC architecture, which is high performance, flexible, programmable, and compiler-independent, is designed for networked media applications. A coarse-grained parallel computing mechanism is employed in this architecture. Mapping this architecture to a specific application is demonstrated through an example in multimedia application. The design is validated in a powerful FPGA, consisting of two CPUs, working at 81MHz and five function units, working at 40.5MHz.
Place, publisher, year, edition, pages
NEW YORK: IEEE , 2008. 41-44 p.
Electrical Engineering, Electronic Engineering, Information Engineering Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-31540DOI: 10.1109/ISSOC.2008.4694877ISI: 000262647700010ScopusID: 2-s2.0-67249088894ISBN: 978-1-4244-2541-9OAI: oai:DiVA.org:kth-31540DiVA: diva2:408584
10th Annual International Symposium on System-on-Chip Tampere, FINLAND, 2008
QC 201104052011-04-052011-03-182015-10-09Bibliographically approved