Scalability of Weak Consistency in NoC based Multicore Architectures
2010 (English)In: IEEE INT SYMP CIRC SYST PROC, New York: IEEE , 2010, 3497-3500 p.Conference paper (Refereed)
In Multicore Network-on-Chip, it is preferable to realize distributed but shared memory (DSM) in order to reuse the huge amount of legacy code and easy programming. Within DSM systems, memory consistency is a critical issue since it affects not only performance but also the correctness of programs. In this paper, we investigate the scalability of the weak consistency model, which may be implemented using a transaction counter. The experimental results compare synchronization latencies for various network sizes, topologies and lock positions in the network. Average synchronization latency rises exponentially for mesh and torus topologies as the network size grows. However, torus improves the synchronization latency in comparison to mesh. For mesh topology network average synchronization latency is also slightly affected by the lock position with respect to the network center.
Place, publisher, year, edition, pages
New York: IEEE , 2010. 3497-3500 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Synchronization, Scalability, Memory consistency, Distributed shared memory
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-32140DOI: 10.1109/ISCAS.2010.5537833ISI: 000287216003180ScopusID: 2-s2.0-77955996105ISBN: 978-142445308-5OAI: oai:DiVA.org:kth-32140DiVA: diva2:409227
International Symposium on Circuits and Systems Nano-Bio Circuit Fabrics and Systems (ISCAS 2010)
QC 201104072011-04-072011-04-072013-02-04Bibliographically approved