3C-SiC MOSFET with High Channel Mobility and CVD Gate Oxide
2011 (English)In: Materials Science Forum, ISSN 0255-5476, Vol. 679-680, 645-648 p.Article in journal (Refereed) Published
3C-SiC MOSFET with 200 cm2/Vs channel mobility was fabricated. High performance device processes were adopted, including room temperature implantation with resist mask, polysilicon-metal gates, aluminium interconnects with titanium and titanium nitride and a specially developed activation anneal at 1600°C in Ar to get a smooth 3C-SiC surface and hence the expected high channel mobility. CVD deposited oxide with post oxidation annealing was investigated to reduce unwanted oxide charges and hence to get a better gate oxide integrity compared to thermally grown oxides. 3C-SiC MOSFETs with 600 V blocking voltage and 10 A drain current were fabricated using the improved processes described above. The MOSFETs assembled with TO-220 PKG indicated specific on-resistances of 5 to 7 mΩcm2.
Place, publisher, year, edition, pages
2011. Vol. 679-680, 645-648 p.
3C-SiC, Capacitance-Voltage Characteristics, Channel Mobility, CVD Deposited Oxide, MOSFET, On Resistance, Post Oxidation Annealing, TZDB
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-32497DOI: 10.4028/www.scientific.net/MSF.679-680.645ISI: 000291673500155OAI: oai:DiVA.org:kth-32497DiVA: diva2:410876
QC 201104152011-04-152011-04-152011-11-16Bibliographically approved