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Worst-Case Flit and Packet Delay Bounds in Wormhole Networks on Chip
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
2009 (English)In: IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, ISSN 0916-8508, E-ISSN 1745-1337, Vol. E92A, no 12, 3211-3220 p.Article in journal (Refereed) Published
Abstract [en]

We investigate per-flow flit and packet worst-case delay bounds in on-chip wormhole networks. Such investigation is essential in order to provide guarantees under worst-case conditions in cost-constrained systems, as required by many hard real-time embedded applications. We first propose analysis models for flow control, link and buffer sharing. Based on these analysis models, we obtain an open-ended service analysis model capturing the combined effect of flow control, link and buffer sharing. With the service analysis model, we compute equivalent service curves for individual flows, and then derive their flit and packet delay bounds. Our experimental results verify that our analytical bounds are correct and tight.

Place, publisher, year, edition, pages
2009. Vol. E92A, no 12, 3211-3220 p.
Keyword [en]
delay bounds, performance analysis, network calculus, network-on-chip
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-32849DOI: 10.1587/transfun.E92.A.3211ISI: 000273190700032Scopus ID: 2-s2.0-79960332548OAI: oai:DiVA.org:kth-32849DiVA: diva2:412817
Note
QC 20110426Available from: 2011-04-26 Created: 2011-04-21 Last updated: 2017-12-11Bibliographically approved

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Lu, Zhonghai

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