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One-Megapixel Monocrystalline-Silicon Micromirror Array on CMOS Driving Electronics Manufactured With Very Large-Scale Heterogeneous Integration
KTH, School of Electrical Engineering (EES), Microsystem Technology.
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2011 (English)In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 20, no 3, 564-572 p.Article in journal (Refereed) Published
Abstract [en]

In this paper, we demonstrate the first high-resolution spatial-light-modulator chip with 1 million tilting micromirrors made of monocrystalline silicon on analog high-voltage complementary metal-oxide-semiconductor driving electronics. This device, as result of a feasibility study, shows good optical and excellent mechanical properties. The micromirrors exhibit excellent surface properties, with a surface roughness below 1-nm root mean square. Actuated micromirrors show no imprinting behavior and operate drift free. Very large-scale heterogeneous integration was used to fabricate the micromirror arrays. The detailed fabrication process is presented in this paper, together with a characterization of the SLM devices. Large arrays of individually controllable micromirrors are the enabling component in high-perfomance mask-writing systems and promising for high throughput deep-ultraviolet maskless lithography systems. The adoption of new materials with enhanced characteristics is critical in meeting the challenging demands with regard to surface quality and operation stability in the future. Very large-scale heterogeneous integration may enable virtually any solid-state material to be integrated together with CMOS electronics. [2010-0272]

Place, publisher, year, edition, pages
2011. Vol. 20, no 3, 564-572 p.
Keyword [en]
Complementary metal-oxide-semiconductor (CMOS) integrated circuits, heterogeneous integration, mirrors, photolithography, silicon, spatial light modulators (SLMs), very large-scale integration, wafer bonding, wafer-scale integration
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:kth:diva-35131DOI: 10.1109/JMEMS.2011.2127454ISI: 000291316000006ScopusID: 2-s2.0-79957993226OAI: diva2:426446
QC 20110623Available from: 2011-06-23 Created: 2011-06-20 Last updated: 2013-08-16Bibliographically approved
In thesis
1. Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
Open this publication in new window or tab >>Wafer-level 3-D CMOS Integration of Very-large-scale Silicon Micromirror Arrays and Room-temperature Wafer-level Packaging
2013 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

This thesis describes the development of wafer-level fabrication and packaging methods for micro-electromechanical (MEMS) devices, based on wafer-bonding.

The first part of the thesis is addressing the development of a wafer-level technology that allows the use of high performance materials, such as monocrystalline silicon, for MEMS devices that are closely integrated on top of sensitive integrated circuits substrates. Monocrystalline silicon has excellent mechanical properties that are hard to achieve otherwise, and therefore it fits well in devices for adaptive optics and maskwriting applications where nanometer precision deflection requirements call for mechanically stable materials. However, the temperature sensitivity of the integrated circuits prohibits the use of monocrystalline silicon with conventional deposition and surface micromachining techniques. Here, heterogeneous 3-D integration by adhesive wafer-bonding is used to fabricate three different types of spatial light modulators, based on micromirror arrays made of monocrystalline silicon; micromirror arrays with vertically moving “piston-type” mirrors and with tilting mirrors made of one functional monocrystalline silicon layer, and vertically moving hidden-hinge micromirror arrays made of two functional monocrystalline silicon layers.

The second part of the thesis addresses the need for room-temperature packaging methods that allow the packaging of liquids or in general heat sensitive devices on wafer-level. A packaging method was developed that is based on a hybrid wafer-bonding approach, combining the compression bonding of gold gaskets with adhesive bonding. The packaging method is first demonstrated for the wafer-level encapsulation of liquids in reservoirs and then applied to packaging a dye-based photonic gas sensor.


Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2013. xi, 126 p.
Trita-EES, 2013:031
National Category
Engineering and Technology
urn:nbn:se:kth:diva-125913 (URN)978-91-7501-843-0 (ISBN)
Public defence
2013-09-06, F3, Lindstedtsvägen 26, KTH, Stockholm, 14:14 (English)

QC 20130816

Available from: 2013-08-16 Created: 2013-08-16 Last updated: 2013-08-19Bibliographically approved

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Lapisa, MartinStemme, GöranNiklaus, Frank
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