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Low Temperature Epitaxy Growth and Kinetic Modeling of SiGe for BiCMOS Application
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

There is an ambition of continuously decreasing thermal budget in CMOS and BiCMOS processing, thus low temperature epitaxy (LTE) (350-650°C) with chemical vapor deposition (CVD) technique in order to have faster process with low cost. One of the growth issues at low temperatures is gas quality where the oxygen and moisture contamination becomes critical for the epilayers quality. If the level amount of contamination is not controlled, the silicon dioxide islands are formed and the oxygen level in the film will be high. This thesis is focused on two different aspects of "LTE".

The first focus of this thesis was to identify the effect of contamination on the strain and quality of the SiGe epilayers (prior and during epitaxy). The samples in this study were exposed to different oxygen and moisture partial pressures (2ppb-250 ppm range) at different exposure temperatures (350-650°C).

The results revealed that presence of contamination even at low ranges (2-100 ppb) is not negligible and affects the strain. Parameters such as O2 exposure temperature and partial pressure, and SiGe layer’s growth temperature impacted the oxygen level and strain in the films. For oxygen levels below 100 ppb, High Resolution Scanning Microscopy (HRSEM) could not detect very small oxide island. By increasing the O2 partial pressure well above 100 ppb, the oxide islands are saturated at 0.08 μm2.

The second focus of this thesis was to model the Si2H6/Ge2H6-based epitaxial growth of SiGe. The model can predict the number of free sites on Si surface, growth rate of Si and SiGe, and the Ge content at low temperature. A good agreement between the model and the experimental data is found. This model can provide the required growth parameters for certain layer profile which is vital to decrease the total number of growth runs for calibration and cause to reduce the total fabrication cost.

Place, publisher, year, edition, pages
2011. , 47 p.
Trita-ICT-EX, 120
URN: urn:nbn:se:kth:diva-37232OAI: diva2:432734
Subject / course
Microelectronics and Applied Physics
Educational program
Master of Science - Nanotechnology
Available from: 2011-08-05 Created: 2011-08-05 Last updated: 2011-08-05Bibliographically approved

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