Digital calibration of gain and linearity in a CMOS RF mixer
2008 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, 2008, 1288-1291 p.Conference paper (Refereed)
This paper presents a new digital calibration technique that allows CMOS Gilbert cell down-conversion mixers to meet their block specifications under large process, temperature and power supply variations. The gain and IIP3 are calibrated by regulating the current of the input differential pair and by switching the loads. IIP2 calibration is achieved by using a novel technique that consists of offset voltages cancellation in the switching pairs. The technique is tested by calibrating a 0.18um CMOS mixer in several corner conditions. It is found that by using this calibration technique, the Gilbert cell mixer can achieve yields comparable to digital circuits, hence making it amenable to AMS SoC integration.
Place, publisher, year, edition, pages
2008. 1288-1291 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0277-674X ; 1-10
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-38371DOI: 10.1109/ISCAS.2008.4541661ISI: 000258532101053ScopusID: 2-s2.0-51749095051ISBN: 978-1-4244-2078-0OAI: oai:DiVA.org:kth-38371DiVA: diva2:437276
IEEE International Symposium on Circuits and Systems Location: Seattle, WA Date: MAY 18-21, 2008