Cluster-based simulated annealing for mapping cores onto 2D mesh networks on chip
2008 (English)In: 2008 IEEE Workshop On Design And Diagnostics Of Electronic Circuits And Systems, Proceedings / [ed] Straube, B; Drutarovsky, M; Renovell, M; Gramata, P; Fischerova, M, 2008, 92-97 p.Conference paper (Refereed)
In Network-on-Chip (NoC) application design, core-to-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle the mapping problem in 2D mesh NoCs. In particular, we combine a clustering technique with the simulated annealing to speed up the convergence to near-optimal solutions. The clustering exploits the connectivity and distance relation in the network architecture as well as the locality and bandwidth requirements in the core communication graph. The annealing is cluster-aware and may be dynamically constrained within clusters. Our experiments suggest that simulated annealing can be effectively used to solve the mapping problem with a scalable size, and the combined strategy improves over the simulated annealing in execution time by up to 30% without compromising the quality of solutions.
Place, publisher, year, edition, pages
2008. 92-97 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-38801DOI: 10.1109/DDECS.2008.4538763ISI: 000256936300020ScopusID: 2-s2.0-50649100909ISBN: 978-1-4244-2276-0OAI: oai:DiVA.org:kth-38801DiVA: diva2:438141
2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS; Bratislava; 16 April 2008 through 18 April 2008