Extending systems-on-chip to the third dimension: Performance, cost and technological tradeoffs
2007 (English)In: IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, 2007, 212-219 p.Conference paper (Refereed)
Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as Wed silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding in optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.
Place, publisher, year, edition, pages
2007. 212-219 p.
, Digest of technical papers - IEEE International Conference on Computer-Aided Design, ISSN 1063-6757 ; 1-2
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-39137DOI: 10.1109/ICCAD.2007.4397268ISI: 000253303700034ScopusID: 2-s2.0-49849099251ISBN: 978-1-4244-1381-2OAI: oai:DiVA.org:kth-39137DiVA: diva2:439674
2007 IEEE/ACM International Conference on Computer-Aided Design, ICCAD; San Jose, CA; 4 November 2007 through 8 November 2007