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Toward a scalable test methodology for 2D-mesh network-on-chips
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0002-8072-1742
2007 (English)In: 2007 Design, Automation & Test In Europe Conference & Exhibition: Vols 1-3, 2007, 367-372 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%.

Place, publisher, year, edition, pages
2007. 367-372 p.
Series
Design, Automation and Test in Europe Conference and Expo, ISSN 1530-1591
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-39126ISI: 000252175700062Scopus ID: 2-s2.0-34548303758ISBN: 978-3-9810801-2-4 (print)OAI: oai:DiVA.org:kth-39126DiVA: diva2:439864
Conference
Design, Automation and Test in Europe Conference and Exhibition Location: Nice, France, Date: APR 16-20, 2007
Available from: 2011-09-09 Created: 2011-09-08 Last updated: 2011-09-09Bibliographically approved

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  • Other locale
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Output format
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