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Increasing NoC performance and utilisation using a Dual Packet Exit strategy
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
2007 (English)In: DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS / [ed] Kubatova, H, LOS ALAMITOS: IEEE COMPUTER SOC , 2007, 511-518 p.Conference paper, Published paper (Refereed)
Abstract [en]

When designing a network the use of buffers is inevitable. Buffers are used at the entry point, inside and at the exits of the network. The usage of these buffers significantly changes the performance of the system. as a whole. In order to enhance the buffer utilisation the concept of letting more than one packet exit the network at every switch each clock cycle is introduced - Dual Packet Exit (DPE). The approach is tried on a 4x4 and a 6x6 mesh. We demonstrate the buffers used in combination with different routing strategies for best effort performance. The result we present shows a 50% reduction in terms of worst case latency and a 30% reduction in terms of average latency as well as an increased throughput both from a system and network perspective. We define the term Operational Efficiency as a measure of the network efficiency and show that it increases by roughly 20 % with the DPE technique.

Place, publisher, year, edition, pages
LOS ALAMITOS: IEEE COMPUTER SOC , 2007. 511-518 p.
Keyword [en]
Computer networks; Electric network topology; Switching circuits; Systems analysis
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-39435DOI: 10.1109/DSD.2007.4341516ISI: 000251463100074Scopus ID: 2-s2.0-47749149537ISBN: 978-0-7695-2978-3 (print)OAI: oai:DiVA.org:kth-39435DiVA: diva2:440384
Conference
10th Euromicro Conference on Digital System Design Architectures, Methods and Tools. Lubeck, GERMANY. AUG 29-31, 2007
Note
QC 20110912Available from: 2011-09-12 Created: 2011-09-09 Last updated: 2011-11-24Bibliographically approved
In thesis
1. Architectural Techniques for Improving Performance in Networks on Chip
Open this publication in new window or tab >>Architectural Techniques for Improving Performance in Networks on Chip
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The main aim of this thesis is to propose enhancing techniques for the performance in Networks on Chips. In addition, a concrete proposal for a protocol stack within our NoC platform Nostrum is presented. Nostrum inherently supports both Best Effort as well as Guaranteed Throughput traffic delivery. It employs a deflective routing scheme for best effort traffic delivery that gives a small footprint of the switches in combination with robustness to disturbances in the network. For the traffic delivery with hard guarantees a TDMA based scheme is used. During the transmission process in a NoC several stages are involved. In the papers included, I propose a set of strategies to enhance the performance in several of these stages. The strategies are summarised as follows

Temporally Disjoint Networks is that a physical network, potentially, can be seen to contain a set of separate networks that a packet can enter dependenton when it enters the physical network. This has the consequence that wecould have different traffic types in the different networks.

Looped containers provide means to set up virtual circuits in networksusing deflective routing. High priority container packets are inserted intothe network to follow a predefined, closed, route between source and destination.At sender side the packets are loaded and sent to the destination where it is unloaded and sent back.

Proximity Congestion Awareness reduces the load of the network by diverting packets away from congested areas. It can increase the maximum trafficload by a factor of 20.

Dual Packet Exit increases the exit bandwidth of the network leading to a50 percent reduction in worst-case latency and a 30 percent reduction inaverage latency as well as a lowered buffer usage.

Priority Based Forced Requeue prematurely lifts out low priority packetsfrom the network to be requeued. Packets that have not yet entered the network compete with packets inside the network which gives tighter boundson admission with a reduction of worst case latencies by 50 percent.

Furthermore, Operational Efficiency is proposed as a measure to quantifyhow effective a network is and is defined as the throughput per buffers used in the system. An increase of the injection of packets into the network to increase the system throughput will have a cost associated to it and can be optimised to save energy.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2011. xxiv, 103 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 11:13
National Category
Communication Systems
Identifiers
urn:nbn:se:kth:diva-48243 (URN)978-91-7501-169-1 (ISBN)
Public defence
2011-12-08, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 13:00 (English)
Opponent
Supervisors
Note
QC 20111124Available from: 2011-11-24 Created: 2011-11-16 Last updated: 2012-01-16Bibliographically approved

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