Design and gate drive considerations for epitaxial 1.2 kV buried grid N-on and N-off JFETs for operation at 250°C
2010 (English)In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2, STAFA-ZURICH: TRANS TECH PUBLICATIONS LTD , 2010, Vol. 645/648, 961-964 p.Conference paper (Refereed)
The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.
Place, publisher, year, edition, pages
STAFA-ZURICH: TRANS TECH PUBLICATIONS LTD , 2010. Vol. 645/648, 961-964 p.
, Materials Science Forum, ISSN 0255-5476 ; 645-648
Buried-grid Vertical Junction Field Effect Transistor (BG VJFET)
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-40814DOI: 10.4028/www.scientific.net/MSF.645-648.961ISI: 000279657600229ScopusID: 2-s2.0-77955436937OAI: oai:DiVA.org:kth-40814DiVA: diva2:442245
13th International Conference on Silicon Carbide and Related Materials. Nurnberg, GERMANY. OCT 11-16, 2009
QC 201110202011-09-202011-09-202015-09-15Bibliographically approved