Delay-balanced smart repeaters for on-chip global signaling
2007 (English)In: 20th International Conference On VLSI Design, Proceedings, 2007, 308-313 p.Conference paper (Refereed)
In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18 mu m technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.
Place, publisher, year, edition, pages
2007. 308-313 p.
, Proceedings of the IEEE International Conference on VLSI Design, ISSN 1063-9667
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-40705DOI: 10.1109/VLSID.2007.62ISI: 000245425300044ScopusID: 2-s2.0-48349140101ISBN: 978-0-7695-2762-8OAI: oai:DiVA.org:kth-40705DiVA: diva2:442667
20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems Location: Bangalore, India, Date: JAN 06-10, 2007