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Delay-balanced smart repeaters for on-chip global signaling
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2007 (English)In: 20th International Conference On VLSI Design, Proceedings, 2007, 308-313 p.Conference paper, Published paper (Refereed)
Abstract [en]

In this paper we propose a smart driver, whose drive strength is dynamically altered depending on the relative bit pattern, by partitioning it into a Main Driver and Assistant Driver. For a higher effective load capacitance both drivers switch, while for a lower effective capacitance the assistant driver is quiet. It is shown that in an UMC 0.18 mu m technology the potential peak power saving, for typical global wire lengths, can be as much 18% with a 12% jitter reduction over a traditional repeater for a data rate of 1Gb/s.

Place, publisher, year, edition, pages
2007. 308-313 p.
Series
Proceedings of the IEEE International Conference on VLSI Design, ISSN 1063-9667
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-40705DOI: 10.1109/VLSID.2007.62ISI: 000245425300044Scopus ID: 2-s2.0-48349140101ISBN: 978-0-7695-2762-8 (print)OAI: oai:DiVA.org:kth-40705DiVA: diva2:442667
Conference
20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems Location: Bangalore, India, Date: JAN 06-10, 2007
Available from: 2011-09-22 Created: 2011-09-20 Last updated: 2011-09-22Bibliographically approved

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