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Sizing of MOS device in LC-tank oscillators
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
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2007 (English)In: 2007 Norchip, 2007, 90-95 p.Conference paper, Published paper (Refereed)
Abstract [en]

Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.

Place, publisher, year, edition, pages
2007. 90-95 p.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-40719DOI: 10.1109/NORCHP.2007.4481046ISI: 000257311000021Scopus ID: 2-s2.0-50249095023ISBN: 978-1-4244-1516-8 (print)OAI: oai:DiVA.org:kth-40719DiVA: diva2:442978
Conference
25th Norchip Conference Location: Aalborg, Denmark, Date: NOV 19-20, 2007
Note

QC 20160427

Available from: 2011-09-23 Created: 2011-09-20 Last updated: 2016-04-27Bibliographically approved
In thesis
1. Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
Open this publication in new window or tab >>Low Noise Oscillator in ADPLL toward Direct-to-RF All-digital Polar Transmitter
2012 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In recent years all-digital or digitally-intensive RF transmitters (TX) have attracted great attention in both literature and industry. The motivation is to implement RF circuits in a manner suiting advanced nanometer CMOS processes. To achieve that, information is encoded in the time-domain rather than voltage amplitude. This enables RF design to also benefit from CMOS process scaling. In this thesis an improved architecture of a digitally-intensive transmitter is proposed and validated experimentally. The techniques to lower oscillator phase noise and all-digital phase-locked loop (ADPLL) quantization noise are discussed and proved by both simulation and measurements.

The impact of device sizing on 1/f^2 phase noise is analyzed and validated by measurements. Seven oscillators in 180-nm CMOS with the same LC-tank, operation frequency and power consumption but different core device width are compared. The conclusion clarify the different suggestions on device sizing in the literature. It is illustrated that tail noise contribution is strongly positive dependent to core device sizing, while the contribution of core devices themselves is weakly dependent. Measurements demonstrate that there is a 14-dB phase noise increase when sizing core devices from 40 um to 280 um in the case of noisy tail current. If tail current is clean, the increase is only 4 dB.  For 1/f^3 phase noise, the investigation reveals that the capacitance modulation is the dominant factor accounting for the 1/f or flick noise up-conversion, which is proved by measurements of 180-nm CMOS designs.   A class-C oscillator with ensured start-up and constant amplitude is presented. It achieves a 3.9-dB phase noise reduction in theory and 5-dB reduction in measurements, compared to a conventional LC-tank oscillator operating at the same frequency and power. With the help of a digital bias voltage and bias current control loop, a 191 Figure-of-Merit (FoM) is achieved, showing the ability for low power and noise application.   The previous oscillator optimization techniques have been applied in designing a digital controlled oscillator (DCO) for an ADPLL. A fine tuning varactor is proposed to reduce quantization noise, achieving a frequency step of only several hundreds Hz. In order to measure this small frequency step when the DCO is free-running, a method based on the narrow-band frequency modulation (FM) theory is proposed. The ADPLL wide-band FM is fulfilled by using a digital two-point modulation so that the modulation bandwidth is not limited by the ADPLL loop dynamic.

Finally an all-digital polar TX is proposed based on an improved architecture. The ADPLL is used for FM while a one-bit low-pass Sigma Delta modulator using the phase modulated ADPLL output as the clock accomplishes amplitude modulation. A simple AND gate is adopted to increase the fundamental power as mixers. A class-D power amplifier stages diliver 6.8-dBm power to antenna through a on-chip band-pass pre-filter. The filter also acts as single-ended to differential-end conversion and matching network.

Place, publisher, year, edition, pages
Stockholm: KTH Royal Institute of Technology, 2012. xi, 97 p.
Series
Trita-ICT-ECS AVH, ISSN 1653-6363 ; 13:03
Keyword
all-digital, digitally-intensive, frequency modualtion, phase modulation, amplitude modulation, polar, transmitter, oscillator, digital controled oscillator, DCO, VCO, voltage controled oscillator, class-C oscillator, class-D PA, ADPLL, phase noise, RF, CMOS.
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-118818 (URN)978-91-7501-643-6 (ISBN)
Public defence
2013-03-13, Sal D, KTH-Forum, Isafjordsgatan 39, Kista, 09:00 (English)
Opponent
Supervisors
Available from: 2013-02-28 Created: 2013-02-28 Last updated: 2013-02-28Bibliographically approved

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