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Support for fine-grained synchronization in shared-memory multiprocessors
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA.
Swedish Institute of Computer Science (SICS), Kista, Sweden.
2007 (English)In: Parallel Computing Technologies, Proceedings / [ed] Victor Malyshkin, Springer Berlin/Heidelberg, 2007, Vol. 4671, 453-467 p.Conference paper (Refereed)
Abstract [en]

It has been already verified that hardware-supported fine-grain synchronization provides a significant performance improvement over coarse-grained synchronization mechanisms, such as barriers. Support for fine-grain synchronization on individual data items becomes notably important in order to efficiently exploit thread-level parallelism available on multi-threading and multi-core processors. Fine-grained synchronization can be achieved using the full/empty tagged shared memory. We define the complete set of synchronizing memory instructions as well as the architecture of the full/empty tagged shared memory that provides support for these operations. We develop a snoopy cache coherency protocol for an SMP with the centralized full/empty tagged memory.

Place, publisher, year, edition, pages
Springer Berlin/Heidelberg, 2007. Vol. 4671, 453-467 p.
, Lecture Notes in Computer Science, ISSN 0302-9743 ; 4671
National Category
Computer Science Computer Engineering
URN: urn:nbn:se:kth:diva-41149DOI: 10.1007/978-3-540-73940-1_45ISI: 000251195200045ScopusID: 2-s2.0-38149047556ISBN: 978-3-540-73939-5OAI: diva2:443453
9th International Conference on Parallel Computing Technologies Location: Pereslavl Zalessky, Russia, Date: SEP 03-07, 2007
QC 20110926Available from: 2011-09-26 Created: 2011-09-23 Last updated: 2012-01-04Bibliographically approved

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