Layered switching for networks on chip
2007 (English)In: 2007 44th ACM/IEEE Design Automation Conference, Vols 1 And 2, 2007, 122-127 p.Conference paper (Refereed)
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture. Synthesis results show that our strategy suggests negligible degradation in hardware speed (1%) and area overhead (7%). Simulation results demonstrate that it achieves higher throughput than wormhole alone while significantly reducing the buffer space required at network nodes when compared with virtual cut-through.
Place, publisher, year, edition, pages
2007. 122-127 p.
, Design Automation Conference DAC, ISSN 0738-100X
network-on-chip, system-on-chip, switching technique
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-41044ISI: 000249725800025ScopusID: 2-s2.0-34547268960ISBN: 978-1-59593-771-1OAI: oai:DiVA.org:kth-41044DiVA: diva2:444823
44th ACM/IEEE Design Automation Conference Location: San Diego, CA Date: JUN 04-08, 2007
QC 201109302011-09-302011-09-232011-09-30Bibliographically approved