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Layered switching for networks on chip
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.ORCID iD: 0000-0003-0061-3475
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
2007 (English)In: 2007 44th ACM/IEEE Design Automation Conference, Vols 1 And 2, 2007, 122-127 p.Conference paper, Published paper (Refereed)
Abstract [en]

We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture. Synthesis results show that our strategy suggests negligible degradation in hardware speed (1%) and area overhead (7%). Simulation results demonstrate that it achieves higher throughput than wormhole alone while significantly reducing the buffer space required at network nodes when compared with virtual cut-through.

Place, publisher, year, edition, pages
2007. 122-127 p.
Series
Design Automation Conference DAC, ISSN 0738-100X
Keyword [en]
network-on-chip, system-on-chip, switching technique
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:kth:diva-41044ISI: 000249725800025Scopus ID: 2-s2.0-34547268960ISBN: 978-1-59593-771-1 (print)OAI: oai:DiVA.org:kth-41044DiVA: diva2:444823
Conference
44th ACM/IEEE Design Automation Conference Location: San Diego, CA Date: JUN 04-08, 2007
Note
QC 20110930Available from: 2011-09-30 Created: 2011-09-23 Last updated: 2011-09-30Bibliographically approved

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Lu, Zhonghai

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