Flexible bus and NoC performance analysis with configurable synthetic workloads
2006 (English)In: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings / [ed] Muthukumar, V, 2006, 681-688 p.Conference paper (Refereed)
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a No C and a bus based platform are analyzed.
Place, publisher, year, edition, pages
2006. 681-688 p.
NoC, bus, performance analysis, simulation, benchmark, synthetic workloads
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-41741DOI: 10.1109/DSD.2006.52ISI: 000242376400092ScopusID: 2-s2.0-34547983104ISBN: 0-7695-2609-8OAI: oai:DiVA.org:kth-41741DiVA: diva2:445133
9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006; Dubrovnik; 30 August 2006 through 1 September 2006
QC 201110032011-10-032011-09-302016-05-11Bibliographically approved