A high level power model for the Nostrum NoC
2006 (English)In: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings / [ed] Muthukumar, V, 2006, 673-676 p.Conference paper (Refereed)
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. The model, which from now on will he called Nos-HPM (Nostrum High-Level Power Model) allows a fast power analysis and is accurate within 5%. System simulations with Nos-HPM run up to 500 times faster than with Power Compiler for a 4 x 4 network. We find a maximum power consumption of 0.7 W for a 4 x 4 mesh and 3.5 W for an 8 x 8 mesh, both implemented in 0.18 mu m UPC CMOS technology. In the worst case the average energy per cycle for a 128-bit packet is 508 pJ, while it is 20 pJ for a payload byte. The power consumption of all the links is equivalent or slightly higher than the power consumption of all the switches. A comparison between our results and some related work is also presented.
Place, publisher, year, edition, pages
2006. 673-676 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-41740DOI: 10.1109/DSD.2006.9ISI: 000242376400090ScopusID: 2-s2.0-34547986791ISBN: 0-7695-2609-8OAI: oai:DiVA.org:kth-41740DiVA: diva2:445152
9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, DSD 2006; Dubrovnik; 30 August 2006 through 1 September 2006
QC 201110032011-10-032011-09-302011-10-03Bibliographically approved