Device integration issues towards 10 nm MOSFETs
2006 (English)In: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, 25-30 p.Conference paper (Refereed)
An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.
Place, publisher, year, edition, pages
NEW YORK, NY: IEEE , 2006. 25-30 p.
, International Conference on Microelectronics-MIEL, ISSN 2159-1660
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-42038DOI: 10.1109/ICMEL.2006.1650891ISI: 000238839700004ScopusID: 2-s2.0-77956550566ISBN: 1-4244-0116-XOAI: oai:DiVA.org:kth-42038DiVA: diva2:446438
25th International Conference on Microelectronics. Belgrade, SERBIA MONTENEG. MAY 14-17, 2006
QC 201110072011-10-072011-10-052012-03-22Bibliographically approved