High-speed pipelined DAC architecture using Gray coding
2006 (English)In: 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, NEW YORK, NY: IEEE , 2006, 113-116 p.Conference paper (Refereed)
This work describes a new architecture suitable for wide-band Digital to Analog Converters (DACs) for System-on-Chip. The architecture use a switched capacitor pipelined D/A converter design with selection inversion based on Gray coded bits. A 95dB DC-gain fully differential folded cascode gain-boosted OTA to be used in each pipelined DAC bit cell has been designed. Two bit Switched-Capacitor cells have been analysed, one amplifier offset-compensated version and one high-speed version. High linearity up to 64dB SFDR is achieved for a 1MHz input sine wave at a 10MHz update frequency of the first DAC bit cell and 20MHz update frequency for the second DAC bit cell. The speed limiting factor is the switch sizes, not the amplifier bandwidths.
Place, publisher, year, edition, pages
NEW YORK, NY: IEEE , 2006. 113-116 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
mplifiers (electronic), Bandwidth, Bits, Capacitors, Electronics engineering, Gain control, Microprocessor chips, Signal encoding, Switching networks
IdentifiersURN: urn:nbn:se:kth:diva-42345DOI: 10.1109/ISCAS.2006.1692535ISI: 000245413500029ScopusID: 2-s2.0-34547291958ISBN: 978-0-7803-9389-9OAI: oai:DiVA.org:kth-42345DiVA: diva2:446839
IEEE International Symposium on Circuits and Systems. Kos, GREECE. MAY 21-24, 2006
QC 201110102011-10-102011-10-102011-10-10Bibliographically approved