Analysis of timing jitter in inverters induced by power-supply noise
2006 (English)In: IEEE DTIS: 2006 International Conference on Design & Test of Integrated Systems in Nanoscale Technology, Proceedings / [ed] Girard, P; Masmoudi, M; Mouine, J; Renovell, M, 2006, 53-56 p.Conference paper (Refereed)
This paper describes the transformation process of power-supply noise (PSN) to timing jitter of inverters. The focus is on the inverters used in multiphase clock-generator circuits (CGCs) commonly needed for Switched-Capacitor (SC) SigmaDelta (E-A) Analog-to-Digital Converters (ADCs). Closed form expressions relating timing jitter and PSN are presented and the results are compared with Monte-Carlo simulations performed in Spectre at 13SEN13-6 transistor model level using the processes ANIS 0.351im and UMC 0.18 mu m. The PSN is assumed to have a white frequency distribution with independent power and ground noise. The results show that the transformation process is approximately linear and that the jitter impact decreases as transistors move deeper into the submicron domain. Furthermore, the transformation process is not symmetrical and is dependent on switching direction, even if the PMOS and NMOS sizings are such that the effects due to difference in hole and electron mobility are mitigated.
Place, publisher, year, edition, pages
2006. 53-56 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-42190DOI: 10.1109/DTIS.2006.1708708ISI: 000242105300011ScopusID: 2-s2.0-46249132829ISBN: 0-7803-9726-6OAI: oai:DiVA.org:kth-42190DiVA: diva2:446911
2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006; Tunis; 5 September 2006 through 7 September 2006
QC 201110102011-10-102011-10-062011-10-10Bibliographically approved