A layered approach to estimating power consumption
2006 (English)In: 24th Norchip Conference, Proceedings / [ed] Johansson, T, IEEE , 2006, 93-98 p.Conference paper (Refereed)
A layered approach to estimating power consumption at the highest level of abstraction is presented. This approach is sufficiently accurate and fast enough to be used as guide for exploring the algorithmic and architectural space. The layers span from use-case level down to gate level. Speed and accuracy come from our ability to relate parameterized transactions at architectural level to switching activity at gate level and to perform architecturally-aware application-level simulation for specific or sweeps of use-cases. That enables us to recreate accurately architectural-level transactions. Additionally, we use preliminary floorplan to factor physical design aspects to improve the accuracy of our estimates. We base our work on the industry standard SPIRIT for specifying IPs and Platforms. Early results of work are also presented.
Place, publisher, year, edition, pages
IEEE , 2006. 93-98 p.
Algorithms, Computer simulation, Parameterization
IdentifiersURN: urn:nbn:se:kth:diva-42435DOI: 10.1109/NORCHP.2006.329252ISI: 000245540900022ScopusID: 2-s2.0-34547356793ISBN: 978-1-4244-0772-9OAI: oai:DiVA.org:kth-42435DiVA: diva2:446972
24th Norchip Conference, 2006; Linkoping; Sweden; 20 November 2006 through 21 November 2006
QC 201110102011-10-102011-10-102014-11-10Bibliographically approved