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A layered approach to estimating power consumption
KTH, School of Information and Communication Technology (ICT), Electronic Systems.
KTH, School of Information and Communication Technology (ICT), Electronic Systems.ORCID iD: 0000-0003-0565-9376
2006 (English)In: 24th Norchip Conference, Proceedings / [ed] Johansson, T, IEEE , 2006, 93-98 p.Conference paper, Published paper (Refereed)
Abstract [en]

A layered approach to estimating power consumption at the highest level of abstraction is presented. This approach is sufficiently accurate and fast enough to be used as guide for exploring the algorithmic and architectural space. The layers span from use-case level down to gate level. Speed and accuracy come from our ability to relate parameterized transactions at architectural level to switching activity at gate level and to perform architecturally-aware application-level simulation for specific or sweeps of use-cases. That enables us to recreate accurately architectural-level transactions. Additionally, we use preliminary floorplan to factor physical design aspects to improve the accuracy of our estimates. We base our work on the industry standard SPIRIT for specifying IPs and Platforms. Early results of work are also presented.

Place, publisher, year, edition, pages
IEEE , 2006. 93-98 p.
Keyword [en]
Algorithms, Computer simulation, Parameterization
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:kth:diva-42435DOI: 10.1109/NORCHP.2006.329252ISI: 000245540900022Scopus ID: 2-s2.0-34547356793ISBN: 978-1-4244-0772-9 (print)OAI: oai:DiVA.org:kth-42435DiVA: diva2:446972
Conference
24th Norchip Conference, 2006; Linkoping; Sweden; 20 November 2006 through 21 November 2006
Note

QC 20111010

Available from: 2011-10-10 Created: 2011-10-10 Last updated: 2014-11-10Bibliographically approved

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Hemani, Ahmed

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Citation style
  • apa
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  • de-DE
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  • nn-NO
  • nn-NB
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  • Other locale
More languages
Output format
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