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Power consumption optimization of dataflow applications on many-core systems
KTH, School of Information and Communication Technology (ICT).
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

With the growing need for high bandwidth digital communications and streaming applications requiring high quality of video and audio encoding, the transition to platforms consisting of hundreds of processors and efficient communication infrastructures is inevitable. DSP applications targeted to such highly parallel platforms are best described by concurrent MoCs to enable the mapping and scheduling process to such architectures.

Such platforms target embedded devices which operate under a very constraint energy budget. This project is about the energy efficient scheduling of DSP applications, described under the dataflow MoC, on many-core platforms. The target platform is the P2012 designed by STMicroelectronics consisting 16 nodes interconnected through a 2D mesh asynchronous NoC. Each node can operateon different voltage and frequency and can accommodate up to 16 processors. The dataflow MoC considered to describe the aforementioned applications is called SDF.

The main advantage gained from this project is the formal description of the energy minimization problem, when such platforms are being considered. We demonstrate the difficulties that arise from these architectures, the insufficiency of the existing energy efficient scheduling approaches and we propose a way to relax this very complex problem so that existing approaches can be applied.

Place, publisher, year, edition, pages
2011. , 78 p.
Trita-ICT-EX, 192
National Category
Engineering and Technology
URN: urn:nbn:se:kth:diva-42477OAI: diva2:447170
Subject / course
Electronic- and Computer Systems
Educational program
Master of Science - System-on-Chip Design
Available from: 2011-10-11 Created: 2011-10-11 Last updated: 2011-10-11Bibliographically approved

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