Switching sensitive driver circuit to combat dynamic delay in on-chip buses
2005 (English)In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation / [ed] Paliouras, V; Vounckx, J; Verkest, D, Springer, 2005, Vol. 3728, 277-285 p.Conference paper (Refereed)
In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it's drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.
Place, publisher, year, edition, pages
Springer, 2005. Vol. 3728, 277-285 p.
, Lecture Notes in Computer Science, ISSN 0302-9743 ; 3728
Delay circuits, Electric power system interconnection, Jitter, Switching
IdentifiersURN: urn:nbn:se:kth:diva-42696ISI: 000233594100029ScopusID: 2-s2.0-33646395654ISBN: 978-354029013-1OAI: oai:DiVA.org:kth-42696DiVA: diva2:447439
15th International Workshop on Power and Timing Modeling, Optimization and Simulation. Leuven, Belgium. Sep 21-23, 2005
QC 201110112011-10-122011-10-112014-12-01Bibliographically approved