Linear-time algorithm for computing minimum checkpoint sets for simulation-based verification of HDL programs
2005 (English)In: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings, IEEE , 2005, 2212-2215 p.Conference paper (Refereed)
Simulation-based verification is a popular method for functional validation of hardware. It is performed by applying a set of tests to the system under consideration and to its reference model, and comparing the results. The effectiveness of a test suite is measured by the fraction of the system covered by the tests. In this paper, we present a technique for selecting a part of the system, called checkpoints, with the property that any set of tests which covers the checkpoints covers the entire system. Thus, by constructing a test suit for the checkpoints, a 100% coverage can be achieved. We present a linear-time algorithm for computing a minimum checkpoint set based on pre- and post-dominator relations of the control flow graph of the HDL program representing the system.
Place, publisher, year, edition, pages
IEEE , 2005. 2212-2215 p.
, IEEE International Symposium on Circuits and Systems, ISSN 0271-4302
Channel capacity, Clustering algorithms, Computation theory, Testing
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-43157DOI: 10.1109/ISCAS.2005.1465061ISI: 000232002402076ScopusID: 2-s2.0-67649126697ISBN: 0-7803-8834-8OAI: oai:DiVA.org:kth-43157DiVA: diva2:448189
IEEE International Symposium on Circuits and Systems (ISCAS). Kobe, Japan. May 23-26, 2005
QC 201110142011-10-142011-10-132012-09-26Bibliographically approved